Nowadays the on-chip operating voltages are generally lower than the voltage applied externally to the chip. Therefore, integrated voltage regulators are required on the chip in order to reduce the external voltage. Said voltage regulators may be based on an n-channel MOS technology, by way of example. In order to be able to sufficiently increase the voltage at the gate of the output transistor—embodied as an NMOS transistor—of the voltage regulator, such series regulators additionally have a charge pump. In comparison with a PMOS transistor, an NMOS transistor as output transistor advantageously affords a better suppression of the input voltage and a lower sensitivity in the event of load fluctuations. These voltage regulators may be formed as three-point regulators, for example, although the voltage at the output of the voltage regulator has a certain ripple. With the aid of a continuous regulator, however, this ripple can be reduced and the voltage regulation can thus be improved. In principle, such circuits, which are also known by the designation low-drop voltage regulators, are designed for a particularly low voltage drop between input and output.
For various reasons and inter alia also because mirroring out or decoupling a partial current is beset with considerable difficulties in the case of a voltage regulator having an NMOS series transistor, hitherto use has been made exclusively of voltage regulators having a PMOS output transistor. In the case of a voltage regulator having a PMOS output transistor, a partial current of the total supply current can be decoupled through simple supplementary connection of a current mirror transistor.
In principle, it is a prerequisite for a current mirror that both transistors, that is to say the transistors P1 and P2 in the exemplary embodiment shown in FIG. 1, see the same control voltage between gate and source. That is to say that the voltage drop UGS between gate and source must be identical in magnitude in the case of both transistors P1 and P2. If the two gate terminals of the two transistors P1 and P2 are then connected to one another, a current mirror arises, the magnitude of the mirrored-out current I2 being determined from the ratio of channel width of the first transistor P1 to channel width of the second transistor P2.
FIG. 1 shows a corresponding current mirror having PMOS transistors as can be used in the case of the aforementioned voltage regulator having a PMOS output transistor. The current mirror comprises a first PMOS transistor P1, which is also simultaneously the series transistor of the voltage regulator, and a second PMOS transistor P2. The two source terminals of the first and second PMOS transistors P1 and P2 are connected to one another. An external supply voltage VDDEXT is present at them. The gate terminals of the two PMOS transistors P1 and P2 are likewise connected to one another. The two transistors P1 and P2 are controlled via the common gate thereby formed. Since the ratio of the channel widths of the two PMOS transistors P1 and P2 is 1:1000, the partial current I2 mirrored out via the second PMOS transistor P2 amounts to 1/1000 of the load current I1 flowing via the first PMOS transistor P1. Consequently, I2=I1:1000 holds true to a first approximation.